1. Technical Field
The embodiments described herein relate to a semiconductor apparatus, and in particular, to an address receiving circuit for a semiconductor apparatus.
2. Related Art
As shown in FIG. 1, a conventional receiving circuit includes an address buffer 10, an MRS latch 20, and an MRS decoder 30.
The address buffer 10 receives a general address “A<0:13>” and a bank address “BA<0:1>” according to a clock signal “CK.”
The MRS latch 20 latches an address “TLA<0:15>” output from the address buffer 10 in response to a pulse signal “MRS,” which is generated according to an MRS (Mode Register Set) command. Since the MRS latch 20 must latch the entire address “TLA<0:15>” output from the address buffer 10, latches are provided by the number of bits of the address “TLA<0:15>.”
The MRS decoder 30 decodes and outputs the address TLAD<0:15> latched by the MRS latch 20 according to the configuration settings information of the particular semiconductor operation mode that the semiconductor apparatus is set to. Examples of configuration settings include burst lengths (e.g., “BL4,” “BL8,” etc.), burst type “BTINT,” CAS latency “CL<2:4>,” and write recovery cycle.
The MRS command is input to initialize a semiconductor apparatus. The MRS command defines the standard of MRS command cycle time (tMRD) such that a prescribed time difference is created between an initial MRS command and a subsequent MRS command. In the case of DDR2 and DDR3, the tMRD defines 2 clocks and 4 clocks.
In a conventional semiconductor apparatus, in order to latch an address input according to the MRS command, the number of latches provided need to match the number of bits of the address. Therefore, a large design layout area is required for the latches.
Even if the address is not input until a successive MRS command is input after the initial MRS command input, the clock may be toggled to latch the address, which can result in unnecessary power consumption.